Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Case

A sequential statement which conditionally executes one branch only, depending on the value of the expression at the top.

Syntax

  [Label:] case Expression is
  when Choices => 
    SequentialStatements...
  when Choices =>
    SequentialStatements...
  ... {any number of when parts}
  end case [Label];

  Choices = Choice | Choice | ...
  Choice = {either}
  ConstantExpression
  Range
  others    {the last branch}
          

Where

See Sequential Statement

Rules

The Expression must not be enclosed in parenthesis. The type of the Expression must be enumeration, integer, physical, or a one dimensional array. Every case of the Expression must be covered once and only once by the Choices.

Things to remember

The | is not the "or" operator; the Choices are not or'd together!

Synthesis

Assignments within case statements generally synthesize to multiplexers. Incomplete assignments (i.e. where outputs remain unassigned for certain input conditions) in unclocked processes synthesize to transparent latches. Incomplete assignments in clocked processes synthesize to recirculation around registers.

Example

  case ADDRESS is
  when 0 =>                  -- Select a single value
    A <= '1';
  when 1 =>
    A <= '1';                -- More than one statement in a branch
    B <= '1';
  when 2 to 15 =>            -- Select a range of ADDRESS values
    C <= '1';
  when 16 | 20 | 24 =>       -- Pick out several ADDRESS values
    B <= '1';
    C <= '1';
    D <= '1';
  when others =>             -- Mop up the rest
    null;
  end case;
          

See Also

If, Select, Null, Range